Amplitude increasing and width reducing circuit unit and pulse signal generating circuit and generator comprising amplitude increasing and width reducing circuit unit

The invention provides an amplitude increasing and width reducing circuit unit and a pulse signal generating circuit and generator comprising the amplitude increasing and width reducing circuit unit. According to the amplitude increasing and width reducing circuit unit, two avalanche transistors which are cascaded are used as a basic unit circuit to construct the nanosecond balance pulse signal generator, and compared with a pulse generating circuit composed of a single avalanche transistor, pulse signals generated by the nanosecond balance pulse signal generator are large in amplitude, the pulse front edges are steep, and circuit reliability is high.