Semiconductor device having reduced leakage current at breakdown and method of fabricating thereof

A semiconductor device having a well, a p well implant bounded at least in part within a substrate by the well, a conductive layer disposed on the substrate, a high voltage n- (HVN-) doped well implanted in the p well implant, a high voltage p doped (HVPD) well implanted in the p well implant, and a...

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Bibliographische Detailangaben
Hauptverfasser: LIEN SHININ, CHEN CHIENUNG, HUANG YIN-FU, LEE MING-TUNG, WU SHYI-YUAN
Format: Patent
Sprache:chi ; eng
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Zusammenfassung:A semiconductor device having a well, a p well implant bounded at least in part within a substrate by the well, a conductive layer disposed on the substrate, a high voltage n- (HVN-) doped well implanted in the p well implant, a high voltage p doped (HVPD) well implanted in the p well implant, and a drain n- well and a source n- well disposed in the HVN- doped well and HVPD well, respectively, is provided. A method of fabricating the semiconductor device is also provided. In certain embodiments, the method of fabricating the semiconductor device is characterized by implanting the HVN- ions at a first tilt angle and/or implanting the HVPD ions at a second tilt angle.