Chip laminated structure and manufacturing method thereof

The invention relates to a chip laminated structure and a manufacturing method thereof. The chip laminated structure comprises a top chip with a lower surface, a first insulating layer covering the lower surface of the top chip, a bottom chip with an upper surface, a second insulating layer covering the upper surface of the bottom chip, a plurality of connecting components between the top chip and the bottom chip, and a protection material between the first insulating layer and the second insulating layer. The plurality of connecting components are used to connect the top chip and the bottom chip in a communication manner. The protection material is connected with the plurality of connecting components so as to form a net structure between the first insulating layer and the second insulating layer. The structure and the method at least provide higher strength and stress buffering to resist chip warping and absorb thermal cycle stress, thereby preventing salient points in the chip laminated structure or a diel