Method for regulating erasing voltage of nonvolatile memory
The invention discloses a method for regulating erasing voltage of a nonvolatile memory. A chip of the nonvolatile memory is provided with memory cells in an array. The method for regulating erasing voltage of the nonvolatile memory comprises the following step of simultaneously performing erasing v...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention discloses a method for regulating erasing voltage of a nonvolatile memory. A chip of the nonvolatile memory is provided with memory cells in an array. The method for regulating erasing voltage of the nonvolatile memory comprises the following step of simultaneously performing erasing voltage regulation on all the memory cells in the chip of the nonvolatile memory. According to the method for regulating the erasing voltage of the nonvolatile memory provided by the invention, all the memory cells in the chip of the nonvolatile memory are simultaneously subjected to erasing voltage regulation, so that electrons in a channel of the nonvolatile memory can be saturated, the reference current is stable, and the regulation accuracy is ensured. |
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