Semiconductor technology, semiconductor structure and package structure thereof
The invention relates to a semiconductor technology, a semiconductor structure and a package structure thereof. The semiconductor technology comprises the following steps: providing a carrier, wherein the carrier has a metal layer, and the metal layer has a plurality of substrate areas and a plurali...
Gespeichert in:
Hauptverfasser: | , , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | GUO ZHIMING LIN GONGAN HE RONGHUA CHEN SHENGHUI |
description | The invention relates to a semiconductor technology, a semiconductor structure and a package structure thereof. The semiconductor technology comprises the following steps: providing a carrier, wherein the carrier has a metal layer, and the metal layer has a plurality of substrate areas and a plurality of lateral areas; forming a first photoresist layer; forming a plurality of bearing parts; removing the first photoresist layer to expose the bearing parts, wherein each bearing part has a bearing surface, and each bearing surface has a first area and a second area; forming a second photoresist layer which exposes the first areas of the bearing surfaces; forming a plurality of joint parts, wherein the joint parts cover the first areas of the bearing surfaces so that the joint parts are enabled to be connected with the bearing parts to form snap bumps; removing the second photoresist layer to expose the snap bumps; and removing the lateral areas of the metal layer to enable a plurality of under-bump metal layers |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN103531491A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN103531491A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN103531491A3</originalsourceid><addsrcrecordid>eNrjZPAPTs3NTM7PSylNLskvUihJTc7Iy8_JT6_UUShGkSkuKQIySotSFRLzUhQKEpOzE9NTkURLMlKLUvPTeBhY0xJzilN5oTQ3g6Kba4izh25qQX58ajFQX2peakm8s5-hgbGpsaGJpaGjMTFqAPqPOCA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor technology, semiconductor structure and package structure thereof</title><source>esp@cenet</source><creator>GUO ZHIMING ; LIN GONGAN ; HE RONGHUA ; CHEN SHENGHUI</creator><creatorcontrib>GUO ZHIMING ; LIN GONGAN ; HE RONGHUA ; CHEN SHENGHUI</creatorcontrib><description>The invention relates to a semiconductor technology, a semiconductor structure and a package structure thereof. The semiconductor technology comprises the following steps: providing a carrier, wherein the carrier has a metal layer, and the metal layer has a plurality of substrate areas and a plurality of lateral areas; forming a first photoresist layer; forming a plurality of bearing parts; removing the first photoresist layer to expose the bearing parts, wherein each bearing part has a bearing surface, and each bearing surface has a first area and a second area; forming a second photoresist layer which exposes the first areas of the bearing surfaces; forming a plurality of joint parts, wherein the joint parts cover the first areas of the bearing surfaces so that the joint parts are enabled to be connected with the bearing parts to form snap bumps; removing the second photoresist layer to expose the snap bumps; and removing the lateral areas of the metal layer to enable a plurality of under-bump metal layers</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140122&DB=EPODOC&CC=CN&NR=103531491A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140122&DB=EPODOC&CC=CN&NR=103531491A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GUO ZHIMING</creatorcontrib><creatorcontrib>LIN GONGAN</creatorcontrib><creatorcontrib>HE RONGHUA</creatorcontrib><creatorcontrib>CHEN SHENGHUI</creatorcontrib><title>Semiconductor technology, semiconductor structure and package structure thereof</title><description>The invention relates to a semiconductor technology, a semiconductor structure and a package structure thereof. The semiconductor technology comprises the following steps: providing a carrier, wherein the carrier has a metal layer, and the metal layer has a plurality of substrate areas and a plurality of lateral areas; forming a first photoresist layer; forming a plurality of bearing parts; removing the first photoresist layer to expose the bearing parts, wherein each bearing part has a bearing surface, and each bearing surface has a first area and a second area; forming a second photoresist layer which exposes the first areas of the bearing surfaces; forming a plurality of joint parts, wherein the joint parts cover the first areas of the bearing surfaces so that the joint parts are enabled to be connected with the bearing parts to form snap bumps; removing the second photoresist layer to expose the snap bumps; and removing the lateral areas of the metal layer to enable a plurality of under-bump metal layers</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2014</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPAPTs3NTM7PSylNLskvUihJTc7Iy8_JT6_UUShGkSkuKQIySotSFRLzUhQKEpOzE9NTkURLMlKLUvPTeBhY0xJzilN5oTQ3g6Kba4izh25qQX58ajFQX2peakm8s5-hgbGpsaGJpaGjMTFqAPqPOCA</recordid><startdate>20140122</startdate><enddate>20140122</enddate><creator>GUO ZHIMING</creator><creator>LIN GONGAN</creator><creator>HE RONGHUA</creator><creator>CHEN SHENGHUI</creator><scope>EVB</scope></search><sort><creationdate>20140122</creationdate><title>Semiconductor technology, semiconductor structure and package structure thereof</title><author>GUO ZHIMING ; LIN GONGAN ; HE RONGHUA ; CHEN SHENGHUI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN103531491A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2014</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>GUO ZHIMING</creatorcontrib><creatorcontrib>LIN GONGAN</creatorcontrib><creatorcontrib>HE RONGHUA</creatorcontrib><creatorcontrib>CHEN SHENGHUI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GUO ZHIMING</au><au>LIN GONGAN</au><au>HE RONGHUA</au><au>CHEN SHENGHUI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor technology, semiconductor structure and package structure thereof</title><date>2014-01-22</date><risdate>2014</risdate><abstract>The invention relates to a semiconductor technology, a semiconductor structure and a package structure thereof. The semiconductor technology comprises the following steps: providing a carrier, wherein the carrier has a metal layer, and the metal layer has a plurality of substrate areas and a plurality of lateral areas; forming a first photoresist layer; forming a plurality of bearing parts; removing the first photoresist layer to expose the bearing parts, wherein each bearing part has a bearing surface, and each bearing surface has a first area and a second area; forming a second photoresist layer which exposes the first areas of the bearing surfaces; forming a plurality of joint parts, wherein the joint parts cover the first areas of the bearing surfaces so that the joint parts are enabled to be connected with the bearing parts to form snap bumps; removing the second photoresist layer to expose the snap bumps; and removing the lateral areas of the metal layer to enable a plurality of under-bump metal layers</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | chi ; eng |
recordid | cdi_epo_espacenet_CN103531491A |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Semiconductor technology, semiconductor structure and package structure thereof |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-05T02%3A27%3A29IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=GUO%20ZHIMING&rft.date=2014-01-22&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN103531491A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |