Method for ranking paths for power optimization of integrated circuit design and corresponding computer program product

Method for ranking paths for power optimization of integrated circuit design and corresponding computer program product

The invention relates to a method for ranking paths for power optimization of an integrated circuit design (10). The method comprises identifying a plurality of paths of the integrated circuit design (10). Each of the paths comprises one or more instances (24, 26, 28, 34, 38, 46) of electronic devic...

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Hauptverfasser: BERKOVITZ ASHER, MALACH GAL, WEISBERGER EYTAN
Format: Patent
Sprache:chi ; eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator BERKOVITZ ASHER
MALACH GAL
WEISBERGER EYTAN
description The invention relates to a method for ranking paths for power optimization of an integrated circuit design (10). The method comprises identifying a plurality of paths of the integrated circuit design (10). Each of the paths comprises one or more instances (24, 26, 28, 34, 38, 46) of electronic devices, thus providing an instance power estimate for each instance in the identified paths, providing, for each identified path, at least one weighted power estimate based on the instance power estimates for the instances (24, 26, 28, 34, 38, 46) in the corresponding path, and providing a ranking of the paths based on the at least one weighted power estimate. The invention also relates to a corresponding computer program product.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN103443738A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN103443738A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN103443738A3</originalsourceid><addsrcrecordid>eNqNjEEKwkAMRbtxIeod4gEEpQXdSlHc6Mp9GWbSGrTJkEkpeHqn4gFcPXj89-fFeEV7SIBWFNTxk7iD6OyRvibKiAoSjXp6OyNhkBaIDTt1hgE8qR_IIGCijsFxVqKKKQqH6ctLHwfLJ1ElN_3EMHhbFrPWvRKuflwU6_PpXl82GKXJufPIaE19223Lqir35eFY_rP5APZlRw4</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for ranking paths for power optimization of integrated circuit design and corresponding computer program product</title><source>esp@cenet</source><creator>BERKOVITZ ASHER ; MALACH GAL ; WEISBERGER EYTAN</creator><creatorcontrib>BERKOVITZ ASHER ; MALACH GAL ; WEISBERGER EYTAN</creatorcontrib><description>The invention relates to a method for ranking paths for power optimization of an integrated circuit design (10). The method comprises identifying a plurality of paths of the integrated circuit design (10). Each of the paths comprises one or more instances (24, 26, 28, 34, 38, 46) of electronic devices, thus providing an instance power estimate for each instance in the identified paths, providing, for each identified path, at least one weighted power estimate based on the instance power estimates for the instances (24, 26, 28, 34, 38, 46) in the corresponding path, and providing a ranking of the paths based on the at least one weighted power estimate. The invention also relates to a corresponding computer program product.</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20131211&amp;DB=EPODOC&amp;CC=CN&amp;NR=103443738A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20131211&amp;DB=EPODOC&amp;CC=CN&amp;NR=103443738A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BERKOVITZ ASHER</creatorcontrib><creatorcontrib>MALACH GAL</creatorcontrib><creatorcontrib>WEISBERGER EYTAN</creatorcontrib><title>Method for ranking paths for power optimization of integrated circuit design and corresponding computer program product</title><description>The invention relates to a method for ranking paths for power optimization of an integrated circuit design (10). The method comprises identifying a plurality of paths of the integrated circuit design (10). Each of the paths comprises one or more instances (24, 26, 28, 34, 38, 46) of electronic devices, thus providing an instance power estimate for each instance in the identified paths, providing, for each identified path, at least one weighted power estimate based on the instance power estimates for the instances (24, 26, 28, 34, 38, 46) in the corresponding path, and providing a ranking of the paths based on the at least one weighted power estimate. The invention also relates to a corresponding computer program product.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjEEKwkAMRbtxIeod4gEEpQXdSlHc6Mp9GWbSGrTJkEkpeHqn4gFcPXj89-fFeEV7SIBWFNTxk7iD6OyRvibKiAoSjXp6OyNhkBaIDTt1hgE8qR_IIGCijsFxVqKKKQqH6ctLHwfLJ1ElN_3EMHhbFrPWvRKuflwU6_PpXl82GKXJufPIaE19223Lqir35eFY_rP5APZlRw4</recordid><startdate>20131211</startdate><enddate>20131211</enddate><creator>BERKOVITZ ASHER</creator><creator>MALACH GAL</creator><creator>WEISBERGER EYTAN</creator><scope>EVB</scope></search><sort><creationdate>20131211</creationdate><title>Method for ranking paths for power optimization of integrated circuit design and corresponding computer program product</title><author>BERKOVITZ ASHER ; MALACH GAL ; WEISBERGER EYTAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN103443738A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2013</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>BERKOVITZ ASHER</creatorcontrib><creatorcontrib>MALACH GAL</creatorcontrib><creatorcontrib>WEISBERGER EYTAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BERKOVITZ ASHER</au><au>MALACH GAL</au><au>WEISBERGER EYTAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for ranking paths for power optimization of integrated circuit design and corresponding computer program product</title><date>2013-12-11</date><risdate>2013</risdate><abstract>The invention relates to a method for ranking paths for power optimization of an integrated circuit design (10). The method comprises identifying a plurality of paths of the integrated circuit design (10). Each of the paths comprises one or more instances (24, 26, 28, 34, 38, 46) of electronic devices, thus providing an instance power estimate for each instance in the identified paths, providing, for each identified path, at least one weighted power estimate based on the instance power estimates for the instances (24, 26, 28, 34, 38, 46) in the corresponding path, and providing a ranking of the paths based on the at least one weighted power estimate. The invention also relates to a corresponding computer program product.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Method for ranking paths for power optimization of integrated circuit design and corresponding computer program product
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-10T04%3A17%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=BERKOVITZ%20ASHER&rft.date=2013-12-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN103443738A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true