Method for ranking paths for power optimization of integrated circuit design and corresponding computer program product

The invention relates to a method for ranking paths for power optimization of an integrated circuit design (10). The method comprises identifying a plurality of paths of the integrated circuit design (10). Each of the paths comprises one or more instances (24, 26, 28, 34, 38, 46) of electronic devices, thus providing an instance power estimate for each instance in the identified paths, providing, for each identified path, at least one weighted power estimate based on the instance power estimates for the instances (24, 26, 28, 34, 38, 46) in the corresponding path, and providing a ranking of the paths based on the at least one weighted power estimate. The invention also relates to a corresponding computer program product.