Method for testing and scheduling soft-core-based three-dimensional SoC (system on chip) under constraint of power consumption

The invention relates to a method for testing and scheduling a soft-core-based three-dimensional SoC under the constraint of power consumption, belongs to the technical field of three-dimensional SoC testing and scheduling, and solves the problem that the testing time of the three-dimensional SoC cannot be optimized under the condition that the three-dimensional SoC simultaneously comprises coarse-grained IP cores and fine-grained IP cores. The method specifically comprises the process as follows: the soft-core-based three-dimensional SoC comprises the coarse-grained IP cores and the fine-grained IP cores; a three-dimensional SoC testing and scheduling mathematical model is established, and xij represents a binary variable; if an i IP core and a j IP core are in parallel test, xij is equal to one, and otherwise, xij is equal to zero; tj is the testing time of the j IP core, and the absolute value of M represents the sum of IP cores in the SoC and shows the maximum value of IP core testing time in parallel tes