Adder

The invention discloses an adder and aims to solve the problem that multi-bit binary addition by a 1-bit full adder in the prior art is time-consuming. The adder comprises a plurality of one-bit full adders serially connected according to a first series rule to form a loop. Each full adder comprises a first addend input end, a second addend input end, a carry value input end, a sum output end, and a carry value output end, wherein the sum output end is used for outputting a sum of a first addend and a second addend, and the carry value output end is used for outputting a carry value obtained by adding the first addend and the second addend. The first series rule includes: the carry value output end of one of each two adjacent full adders is connected with the carry value input end of the other full adder.