Programmable controller

Provided is a programmable controller with which pipeline processing interrupts arising from read-modify-write operations, which occur frequently in programmable controllers comprising ladder language bit operation processors, are avoided. A pipeline stage (execution stage (EX)) which carries out bit operations and bit data merges is disposed after a pipeline stage (read stage (R)) which loads data subject to read-modify-write in a buffer register (141) and retains the address of the subject data in an address retention circuit (22), and thereafter, a pipeline stage (write stage (W)) which stores the merge result at the address that is retained at the read stage (R) is disposed.