Dummy flip chip bumps for reducing stress
A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI...
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| creator | WU SHENGYU KUO TINHAO CHUANG CHITA CHEN CHENSHIEN |
| description | A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. The invention provides the dummy flip chip bumps for reducing stress. |
| format | Patent |
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A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. The invention provides the dummy flip chip bumps for reducing stress.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130306&DB=EPODOC&CC=CN&NR=102956590A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130306&DB=EPODOC&CC=CN&NR=102956590A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WU SHENGYU</creatorcontrib><creatorcontrib>KUO TINHAO</creatorcontrib><creatorcontrib>CHUANG CHITA</creatorcontrib><creatorcontrib>CHEN CHENSHIEN</creatorcontrib><title>Dummy flip chip bumps for reducing stress</title><description>A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. The invention provides the dummy flip chip bumps for reducing stress.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNB0Kc3NrVRIy8ksUEjOABJJpbkFxQpp-UUKRakppcmZeekKxSVFqcXFPAysaYk5xam8UJqbQdHNNcTZQze1ID8-tbggMTk1L7Uk3tnP0MDI0tTM1NLA0ZgYNQDwYCiY</recordid><startdate>20130306</startdate><enddate>20130306</enddate><creator>WU SHENGYU</creator><creator>KUO TINHAO</creator><creator>CHUANG CHITA</creator><creator>CHEN CHENSHIEN</creator><scope>EVB</scope></search><sort><creationdate>20130306</creationdate><title>Dummy flip chip bumps for reducing stress</title><author>WU SHENGYU ; KUO TINHAO ; CHUANG CHITA ; CHEN CHENSHIEN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN102956590A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2013</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>WU SHENGYU</creatorcontrib><creatorcontrib>KUO TINHAO</creatorcontrib><creatorcontrib>CHUANG CHITA</creatorcontrib><creatorcontrib>CHEN CHENSHIEN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WU SHENGYU</au><au>KUO TINHAO</au><au>CHUANG CHITA</au><au>CHEN CHENSHIEN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Dummy flip chip bumps for reducing stress</title><date>2013-03-06</date><risdate>2013</risdate><abstract>A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. The invention provides the dummy flip chip bumps for reducing stress.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Dummy flip chip bumps for reducing stress |
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