Dummy flip chip bumps for reducing stress

Dummy flip chip bumps for reducing stress

A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: WU SHENGYU, KUO TINHAO, CHUANG CHITA, CHEN CHENSHIEN
Format: Patent
Sprache:chi ; eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. The invention provides the dummy flip chip bumps for reducing stress.