Method for designing high reliability and embedded type minimum central processing unit (CPU) core applicable to aerospace field and based on field programmable gate array (FPGA)

The invention discloses a method for designing a high reliability and embedded type minimum central processing unit (CPU) core which is applicable to the aerospace field and based on field programmable gate array (FPGA). The method includes writing a program by a simulated assembly language in advance, converting the program to a machine code in a Binary mode, writing the machine code into a programmable read only memory (PROM), reading data in the PROM according to the program, subjecting the read data to a separation of instructions and target sources, identifying the types of the instructions and the target sources, performing arithmetic logic operation of the data, placing an operation result into a designated place, and finally performing read-write operation of external data according to the instructions. Compared with methods in the prior art, the method has the advantages that small FPGA resources are utilized, the resource spending of the core is over ten times lower than that of existing 80C51 core,