Wafer with intrinsic semiconductor layer

The present invention relates to a method for the manufacture of a wafer, comprising the steps of providing a doped layer (6) on a semiconductor substrate (5); providing a first intrinsic semiconductor layer (7) on the doped layer; providing a buried oxide layer (9) on the first semiconductor layer; and providing a second semiconductor layer (3) on the buried oxide layer. In a first region (A) of the wafer, DRAM devices are formed with capacitor trenches (10) extruding into the doped layer (6). In a second region (B) of the wafer, logic TFTs (13) are formed. The first semiconductor layer (7) is doped at locations below the TFTs. These doped regions are provided with contacts (14) for back-biasing the TFTs.