Method for manufacturing built-in stress nanowire and semiconductor

The invention provides a method for manufacturing a built-in stress nanowire and a semiconductor. The method uses a gate-last process (Gate-last), the lateral face of an NWFET area is protected through an amorphous carbon layer when a grid electrode area is etched, the reverse stress direction borne by the nanowire (SiNW) of the grid electrode area is in the horizontal direction at the time so that the problem that reverse built-in stress of the semiconductor nanowire is not in the horizontal direction is solved, disposition which possibly occurs on the middle portion of the semiconductor nanowire is avoided, even the breaking problem can be solved. The upper surface of a source drain PAD is higher than the SiNW, so that upper surfaces of the source drain and the grid electrode are in a same plane, a grid electrode lateral wall process is not needed, and process flows are simplified.