Method for manufacturing semiconductor structure and vertical channel memory structure

The invention relates to a method for manufacturing a semiconductor structure and a vertical channel memory structure. The method comprises the following steps of: preparing the vertical channel memory structure for filling a physical isolation channel defined in the vertical channel memory structure, wherein the physical isolation channel is defined between adjacent active structures and extended in the first direction, and the active structures are also defined in passages which are opposite to two sides of the physical isolation channel and adjacent to the active structures; and applying a plurality of dielectric layers (such as silicon oxide, silicon nitride and silicon oxide (ONO) layers), a polycrystalline silicon cushion layer and/or an oxide film for filling the physical isolation channel. The invention also provides the vertical channel memory structure. By the method, a small space in a memory array can be filled in a relatively simple and economical mode, and particularly the physical isolation cha