BGA footprint pattern for increasing number of routing channels per PCB layer

The present invention discloses a BGA footprint pattern for increasing number of routing channels per PCB layer. The printed circuit board (PCB) includes a ball grid array (BGA). The PCB further includes a first BGA pad having a circular shape, and a first via having a circular shape, wherein the ci...

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Hauptverfasser: YUE PING, CLEVELAND JOHN, SIDDHAYE SHREERAM, SRINIVAS CHEBROLU, VENKATARAMAN SRINIVAS, REYNOV BORIS
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creator YUE PING
CLEVELAND JOHN
SIDDHAYE SHREERAM
SRINIVAS CHEBROLU
VENKATARAMAN SRINIVAS
REYNOV BORIS
description The present invention discloses a BGA footprint pattern for increasing number of routing channels per PCB layer. The printed circuit board (PCB) includes a ball grid array (BGA). The PCB further includes a first BGA pad having a circular shape, and a first via having a circular shape, wherein the circular shape of the first via overlaps a portion of the circular shape of the first BGA pad and is rotated diagonally relative to a center of the first BGA pad. The PCB also includes a second BGA pad having a circular shape, and a second via having a circular shape, wherein the circular shape of the second via overlaps a portion of the circular shape of the second BGA pad and is rotated diagonally relative to a center of the second pad, and wherein a center of the second via is located at a first distance from the center of the first via and at a first angle relative to an axis that crosses a center of the first via.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN102111957A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN102111957A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN102111957A3</originalsourceid><addsrcrecordid>eNrjZPB1cndUSMvPLykoyswrUShILClJLcoDihQpZOYlF6UmFmfmpSvkleYmpRYp5KcpFOWXloBEkjMS8_JSc4oVCoDiAc5OCjmJlalFPAysaYk5xam8UJqbQdHNNcTZQze1ID8-tbggMTk1L7Uk3tnP0MDI0NDQ0tTc0ZgYNQCV-DWM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>BGA footprint pattern for increasing number of routing channels per PCB layer</title><source>esp@cenet</source><creator>YUE PING ; CLEVELAND JOHN ; SIDDHAYE SHREERAM ; SRINIVAS CHEBROLU ; VENKATARAMAN SRINIVAS ; REYNOV BORIS</creator><creatorcontrib>YUE PING ; CLEVELAND JOHN ; SIDDHAYE SHREERAM ; SRINIVAS CHEBROLU ; VENKATARAMAN SRINIVAS ; REYNOV BORIS</creatorcontrib><description>The present invention discloses a BGA footprint pattern for increasing number of routing channels per PCB layer. The printed circuit board (PCB) includes a ball grid array (BGA). The PCB further includes a first BGA pad having a circular shape, and a first via having a circular shape, wherein the circular shape of the first via overlaps a portion of the circular shape of the first BGA pad and is rotated diagonally relative to a center of the first BGA pad. The PCB also includes a second BGA pad having a circular shape, and a second via having a circular shape, wherein the circular shape of the second via overlaps a portion of the circular shape of the second BGA pad and is rotated diagonally relative to a center of the second pad, and wherein a center of the second via is located at a first distance from the center of the first via and at a first angle relative to an axis that crosses a center of the first via.</description><language>chi ; eng</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS</subject><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20110629&amp;DB=EPODOC&amp;CC=CN&amp;NR=102111957A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20110629&amp;DB=EPODOC&amp;CC=CN&amp;NR=102111957A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YUE PING</creatorcontrib><creatorcontrib>CLEVELAND JOHN</creatorcontrib><creatorcontrib>SIDDHAYE SHREERAM</creatorcontrib><creatorcontrib>SRINIVAS CHEBROLU</creatorcontrib><creatorcontrib>VENKATARAMAN SRINIVAS</creatorcontrib><creatorcontrib>REYNOV BORIS</creatorcontrib><title>BGA footprint pattern for increasing number of routing channels per PCB layer</title><description>The present invention discloses a BGA footprint pattern for increasing number of routing channels per PCB layer. The printed circuit board (PCB) includes a ball grid array (BGA). The PCB further includes a first BGA pad having a circular shape, and a first via having a circular shape, wherein the circular shape of the first via overlaps a portion of the circular shape of the first BGA pad and is rotated diagonally relative to a center of the first BGA pad. The PCB also includes a second BGA pad having a circular shape, and a second via having a circular shape, wherein the circular shape of the second via overlaps a portion of the circular shape of the second BGA pad and is rotated diagonally relative to a center of the second pad, and wherein a center of the second via is located at a first distance from the center of the first via and at a first angle relative to an axis that crosses a center of the first via.</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPB1cndUSMvPLykoyswrUShILClJLcoDihQpZOYlF6UmFmfmpSvkleYmpRYp5KcpFOWXloBEkjMS8_JSc4oVCoDiAc5OCjmJlalFPAysaYk5xam8UJqbQdHNNcTZQze1ID8-tbggMTk1L7Uk3tnP0MDI0NDQ0tTc0ZgYNQCV-DWM</recordid><startdate>20110629</startdate><enddate>20110629</enddate><creator>YUE PING</creator><creator>CLEVELAND JOHN</creator><creator>SIDDHAYE SHREERAM</creator><creator>SRINIVAS CHEBROLU</creator><creator>VENKATARAMAN SRINIVAS</creator><creator>REYNOV BORIS</creator><scope>EVB</scope></search><sort><creationdate>20110629</creationdate><title>BGA footprint pattern for increasing number of routing channels per PCB layer</title><author>YUE PING ; CLEVELAND JOHN ; SIDDHAYE SHREERAM ; SRINIVAS CHEBROLU ; VENKATARAMAN SRINIVAS ; REYNOV BORIS</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN102111957A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2011</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>YUE PING</creatorcontrib><creatorcontrib>CLEVELAND JOHN</creatorcontrib><creatorcontrib>SIDDHAYE SHREERAM</creatorcontrib><creatorcontrib>SRINIVAS CHEBROLU</creatorcontrib><creatorcontrib>VENKATARAMAN SRINIVAS</creatorcontrib><creatorcontrib>REYNOV BORIS</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YUE PING</au><au>CLEVELAND JOHN</au><au>SIDDHAYE SHREERAM</au><au>SRINIVAS CHEBROLU</au><au>VENKATARAMAN SRINIVAS</au><au>REYNOV BORIS</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>BGA footprint pattern for increasing number of routing channels per PCB layer</title><date>2011-06-29</date><risdate>2011</risdate><abstract>The present invention discloses a BGA footprint pattern for increasing number of routing channels per PCB layer. The printed circuit board (PCB) includes a ball grid array (BGA). The PCB further includes a first BGA pad having a circular shape, and a first via having a circular shape, wherein the circular shape of the first via overlaps a portion of the circular shape of the first BGA pad and is rotated diagonally relative to a center of the first BGA pad. The PCB also includes a second BGA pad having a circular shape, and a second via having a circular shape, wherein the circular shape of the second via overlaps a portion of the circular shape of the second BGA pad and is rotated diagonally relative to a center of the second pad, and wherein a center of the second via is located at a first distance from the center of the first via and at a first angle relative to an axis that crosses a center of the first via.</abstract><oa>free_for_read</oa></addata></record>
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subjects CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
title BGA footprint pattern for increasing number of routing channels per PCB layer
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T15%3A16%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=YUE%20PING&rft.date=2011-06-29&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN102111957A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true