Method for compiling regular expression by proportionally dividing into two groups

The invention provides a method for compiling a regular expression by proportionally dividing into two groups. In the method, resources outside chips are fully utilized, so that a field-programmable gate array (FPGA) can perform matching in two paths; groups are divided by adopting a max-cut method, so that n regular expressions generate two groups of deterministic finite automata (DFA) with uniform state numbers, thus the space complexity of the regular expressions is reduced. Therefore, the real time property is not reduced while the hardware space is not changed, and the quantity of the regular expressions processed by the hardware is increased as many as possible.