Synchronous first input first output (FIFO) circuit system

The invention discloses a synchronous first input first output (FIFO) circuit system, comprising a plurality of basic storage cell circuits, wherein the basic storage cell circuits are connected in sequence in a cascading mode; congestion control output of the former basic storage cell circuit is taken as congestion control input of the latter basic storage cell circuit; the former congestion control input of a first basic storage cell circuit is 0, namely, the former congestion control input of the first basic storage cell circuit is non-congestion; the congestion control output of the last basic storage cell circuit is hung; the data output of the latter basic storage cell circuit is taken as input for the data source 1 of the former basic storage cell circuit; and the input for the data source 1 of the last basic storage cell circuit is 0. The system can fast customize domain, optimize area of an integrated circuit chip, and is applied to logic designs such as a memory management module and the like.