Balance error elimination type high-precision digital phase locking method

The invention discloses a balance error elimination type high-precision digital phase locking method. The method comprises the following steps of: (1) performing d and q coordinate transformation on a three-phase instantaneous sample value to obtain the ith phase of given phase value theta i; obtaining a phase difference signal delta (delta) v according to the given phase value theta i and a phase tracking output value theta v; locking the phase difference signal delta (delta) v into angular frequency omega of an input signal by using a PI regulator; and performing integration on the angular frequency omega to obtain the ith phase of phase angle Itheta1; (2) multiplying the ith phase of instantaneous sample value serving as the input signal by a sin (t) data pool and a cos (t) data pool to obtain Uin-sin (t) and Uin-cos (t) corresponding to the ith phase in the step (1) respectively; performing periodic averaging on the obtained results to obtain XC and YC respectively, wherein the phase angle IItheta2 of the