Ic chip package and forming method

The present invention relates to an IC chip package and a forming method. A structure includes a solder element for electrically coupling a substrate of the integrated circuit (IC) chip package and a printed circuit board (PCB); and a first electrical property altering, substantially planar member p...

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Hauptverfasser: BEHUN J. RICHARD, STONE DAVID B
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creator BEHUN J. RICHARD
STONE DAVID B
description The present invention relates to an IC chip package and a forming method. A structure includes a solder element for electrically coupling a substrate of the integrated circuit (IC) chip package and a printed circuit board (PCB); and a first electrical property altering, substantially planar member positioned between the solder element and at least one of a landing pad of the substrate and a landing pad of the PCB. In another embodiment, the electrical property altering, planar member can be applied to the solder element(s) between the IC chip and the package substrate.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN101930960A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN101930960A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN101930960A3</originalsourceid><addsrcrecordid>eNrjZFDyTFZIzsgsUChITM5OTE9VSMxLUUjLL8rNzEtXyE0tychP4WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcVAjal5qSXxzn6GBoaWxgaWZgaOxsSoAQBq9iVl</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Ic chip package and forming method</title><source>esp@cenet</source><creator>BEHUN J. RICHARD ; STONE DAVID B</creator><creatorcontrib>BEHUN J. RICHARD ; STONE DAVID B</creatorcontrib><description>The present invention relates to an IC chip package and a forming method. A structure includes a solder element for electrically coupling a substrate of the integrated circuit (IC) chip package and a printed circuit board (PCB); and a first electrical property altering, substantially planar member positioned between the solder element and at least one of a landing pad of the substrate and a landing pad of the PCB. In another embodiment, the electrical property altering, planar member can be applied to the solder element(s) between the IC chip and the package substrate.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20101229&amp;DB=EPODOC&amp;CC=CN&amp;NR=101930960A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20101229&amp;DB=EPODOC&amp;CC=CN&amp;NR=101930960A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BEHUN J. RICHARD</creatorcontrib><creatorcontrib>STONE DAVID B</creatorcontrib><title>Ic chip package and forming method</title><description>The present invention relates to an IC chip package and a forming method. A structure includes a solder element for electrically coupling a substrate of the integrated circuit (IC) chip package and a printed circuit board (PCB); and a first electrical property altering, substantially planar member positioned between the solder element and at least one of a landing pad of the substrate and a landing pad of the PCB. In another embodiment, the electrical property altering, planar member can be applied to the solder element(s) between the IC chip and the package substrate.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFDyTFZIzsgsUChITM5OTE9VSMxLUUjLL8rNzEtXyE0tychP4WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcVAjal5qSXxzn6GBoaWxgaWZgaOxsSoAQBq9iVl</recordid><startdate>20101229</startdate><enddate>20101229</enddate><creator>BEHUN J. RICHARD</creator><creator>STONE DAVID B</creator><scope>EVB</scope></search><sort><creationdate>20101229</creationdate><title>Ic chip package and forming method</title><author>BEHUN J. RICHARD ; STONE DAVID B</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN101930960A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2010</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>BEHUN J. RICHARD</creatorcontrib><creatorcontrib>STONE DAVID B</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BEHUN J. RICHARD</au><au>STONE DAVID B</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Ic chip package and forming method</title><date>2010-12-29</date><risdate>2010</risdate><abstract>The present invention relates to an IC chip package and a forming method. A structure includes a solder element for electrically coupling a substrate of the integrated circuit (IC) chip package and a printed circuit board (PCB); and a first electrical property altering, substantially planar member positioned between the solder element and at least one of a landing pad of the substrate and a landing pad of the PCB. In another embodiment, the electrical property altering, planar member can be applied to the solder element(s) between the IC chip and the package substrate.</abstract><oa>free_for_read</oa></addata></record>
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language chi ; eng
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Ic chip package and forming method
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-27T05%3A11%3A33IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=BEHUN%20J.%20RICHARD&rft.date=2010-12-29&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN101930960A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true