Transistor test device and method

The invention provides a transistor test device and method, belonging to the technical field of microelectronics. The transistor test device comprises a routing circuit, a logic gate chain circuit and an output buffer circuit, wherein the routing circuit is used to receive routing signals and input signals and control the paths of the input signals according to the routing signals; the logic gatechain circuit is coupled with the routing circuit and ensures that signals pass through the logic gate chain circuit to form tested signals; the logic gate chain circuit is a cascade circuit composedof an even number of cascaded gate circuits, each gate circuit comprises a transistor to be tested; and the output buffer circuit is coupled with the logic gate chain circuit and the routing circuit respectively and used to receive the middle signals from the logic gate chain circuit or the routing circuit and output the buffered output result. By adopting the technical scheme of the invention, the transistor test device a