Clock circuit for a digital circuit
A method of saving power in a digital circuit driven by a clock running at a rate R, comprising reducing said rate R to a lower rate R' during periods when said digital circuit is operating at a capacity less than its maximum capacity, and wherein the change from rate R to rate R' is carri...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | A method of saving power in a digital circuit driven by a clock running at a rate R, comprising reducing said rate R to a lower rate R' during periods when said digital circuit is operating at a capacity less than its maximum capacity, and wherein the change from rate R to rate R' is carried out as a smooth transition. |
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