Syndrome computing circuit in RS (Reed-Solomon) error correcting code decoder and computing method thereof

The invention provides a syndrome computing circuit in a RS error correcting code decoder and a computing method thereof. The syndrome computing circuit comprises a data storage, a multiplying unit and an adder, wherein the data storage at least comprises 2t memory addresses and is used for storing 2t data units; the multiplying unit is used for multiplying the data unit of the ith memory addressread out from the data storage and alphai in sequence so as to acquire a multiplying result, wherein i is an integral and is not less than 1 but is not more than 2t; the adder is used for adding the multiplying result and j+1th codon rN-1-j in N codons input to the syndrome computing circuit so as to acquire an adding result and saving the adding result to the ith memory address of the data storage, wherein j is the frequency of reding all 2t memory addresses of the data storage, and j is an integral and is not less than 1 but is not greater than N-1. Through the settings, the syndrome computing circuit in an RS error