Substrate and chip package structure

The invention discloses a substrate for carrying a chip and a chip package structure. The substrate comprises a first surface and a lead layer, wherein the lead layer is arranged on the first surface, and at least one region without wiring is formed on the lead layer. When the chip is carried by the substrate, the first surface of the substrate faces to the active surface of the chip, the lead layer is electrically connected with the chip, and a fuse setting region on the active surface of the chip is vertically projected in the projection region formed on the first surface of the substrate, and the projection region is located in the range of the at least one region without wiring.