Stacked type chip package structure

The invention provides a chip package structure and a stacked type chip package structure. The stacked type chip package structure employs a substrate having a pseudo-cavity or a keep-out zone at oneside or both sides thereof. Through the pattern arrangement of the wiring layer and the solder mask layer, the thickness of the entire stacked type chip package structure is effectively reduced as lower wire loops and a thinner mold-cap can be achieved by mounting the chip within the depressed keep-out zone. In particular, the double-sided chip package structures are suitable for package on package structures adopted by mobile applications.