Manufacturing method of stacked chip package structure

The invention discloses a manufacturing method of a stacked chip package structure. The method comprises the following steps: providing a substrate first; adhering a first chip and a second chip abovethe substrate, wherein, the second chip is stacked above the first chip; connecting a first bonding wire between a second bonding pad of the second chip and a first area of a first bonding pad of thefirst chip; and connecting a second bonding wire between a second area of the first bonding pad of the first chip and metal contacts of the substrate. Accordingly, the manufacturing method can help greatly reduce the overall volume, effectively solve the problem of various bonding wires, and reduce the occupying volume of bonding pads of the substrate and the number of the bonding pads, thus reducing the complexity of substrate circuit layout.