Serial communication interface with low clock skew
A communication interface for use in an integrated circuit comprises a clock root circuit (110) configured to receive the clock reference signal and to generate a clock tree signal. A first lane circuit (220b) is coupled to the clock root circuit and configured to receive the clock tree signal and a...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | A communication interface for use in an integrated circuit comprises a clock root circuit (110) configured to receive the clock reference signal and to generate a clock tree signal. A first lane circuit (220b) is coupled to the clock root circuit and configured to receive the clock tree signal and a select signal for selecting a clock signal for a first interface circuit. A second lane circuit (220a) is coupled to the first lane circuit and configured to receive the clock tree signal and a select signal for selecting a clock signal for a second interface circuit. In one embodiment, each lane circuit includes a buffer (222) configured to receive the clock tree signal and a multiplexer (228) configured to selectively deliver the clock tree signal to the interface circuit. Advantages of the invention include a modular construction of a communication interface having low clock skew. |
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