Semiconductor memory

The present invention relates to a semiconductor memory comprising a memory core having a memory cell that requires a refresh for data retention; a refresh control circuit that generates at predetermined intervals a refresh command to refresh said memory cell; a sub state machine that issues a refresh permission, a read permission, and a write permission to operate said memory core, in accordance with the refresh command, and a read command and a write command supplied from exterior, respectively; and a main state machine that makes said memory core perform a refresh operation according to the refresh permission, perform a read operation according to the read permission, and perform a write operation according to the write permission, wherein:; said sub state machine has a ready state and a reserve state, the ready state being a state to which the sub state machine makes a transition when no read command is supplied, the reserve state being a state to which the sub state machine makes a transition from the re