True/complement circuit and processor
The invention relates to an integrated circuit, comprising a data node, an output node and a setting logic coupled with the data nodes and the output nodes. The setting logic changes the state of theoutput node by responding to the change on the state of the data node. The integrated circuit also co...
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| creator | SEEWANN ED |
| description | The invention relates to an integrated circuit, comprising a data node, an output node and a setting logic coupled with the data nodes and the output nodes. The setting logic changes the state of theoutput node by responding to the change on the state of the data node. The integrated circuit also comprises a reset transistor coupled with the data node for resetting the data node to a first stateby responding to the conversion of a time sequence signal; an input transistor coupled with the data node for affirming the data node to a second state by responding to a received data signal; and a reset logic coupled between the output node and the data node, wherein, if the output node reaches to the setting state, the first reset logic resets the output node to the initial state by respondingto the reset of the data node. The integrated circuit also comprises a feedback logic coupled between the output node and the reset input node of the reset logic, and the feedback logic limits the duration of the operation of t |
| format | Patent |
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The setting logic changes the state of theoutput node by responding to the change on the state of the data node. The integrated circuit also comprises a reset transistor coupled with the data node for resetting the data node to a first stateby responding to the conversion of a time sequence signal; an input transistor coupled with the data node for affirming the data node to a second state by responding to a received data signal; and a reset logic coupled between the output node and the data node, wherein, if the output node reaches to the setting state, the first reset logic resets the output node to the initial state by respondingto the reset of the data node. The integrated circuit also comprises a feedback logic coupled between the output node and the reset input node of the reset logic, and the feedback logic limits the duration of the operation of t</description><language>chi ; eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; PULSE TECHNIQUE ; STATIC STORES</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100609&DB=EPODOC&CC=CN&NR=101197562B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100609&DB=EPODOC&CC=CN&NR=101197562B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SEEWANN ED</creatorcontrib><title>True/complement circuit and processor</title><description>The invention relates to an integrated circuit, comprising a data node, an output node and a setting logic coupled with the data nodes and the output nodes. The setting logic changes the state of theoutput node by responding to the change on the state of the data node. The integrated circuit also comprises a reset transistor coupled with the data node for resetting the data node to a first stateby responding to the conversion of a time sequence signal; an input transistor coupled with the data node for affirming the data node to a second state by responding to a received data signal; and a reset logic coupled between the output node and the data node, wherein, if the output node reaches to the setting state, the first reset logic resets the output node to the initial state by respondingto the reset of the data node. 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| language | chi ; eng |
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| subjects | BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE STATIC STORES |
| title | True/complement circuit and processor |
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