Efficient video decoding accelerator

The present invention relates to a decoding apparatus and method for decoding compressed video data having a plurality of video frames with a plurality of blocks, wherein the video frames are split in a first predetermined direction into at least two stripes whose width does not exceed a hardware prediction line size. Then, coefficient prediction is performed on one of the at least two stripes toprovide a predictor in a second predetermined direction for at least one other of the at least two stripes, the second predetermined direction being perpendicular to the first predetermined direction. Additionally, fake blocks are generated to be inserted into the at least one other of said at least two stripes in order to initialize prediction in the second predetermined direction. Thereby, hardware accelerators with fixed processing width can be used in a more flexible manner.