Multiple reference clock synthesizer for frequency division of source clock and the method

A clock synthesizer (100) for dividing a source clock by N.R including a logic circuit, a delay line (103), a select circuit, an accumulator (113), and a clock divider circuit. The logic circuit divides N.R by 2M to get NNEW.RNEW in which NNEW is zero and RNEW is at least 0.5. The delay line receives a first clock and has multiple delay taps (0, 1, 2), where the first clock is based on the sourceclock. The select circuit selects the delay taps based on a tap select value and provides a delayed clock. The accumulator adds RNEW for each cycle of the delayed clock and performs a modulo functionon a sum value to generate the tap select value. The clock divider circuit transitions an output clock based on selected transitions of the delayed clock, which is achieved by dividing the first clock or the delayed clock by 2M-1.