Transistor capable of boosting electro-static discharge tolerance

The invention provides a layout method of a transistor capable of improving static discharge tolerance, comprising the definition of a first conduction type protective ring area, the definition of a first strip type second conduction type diffusion zone and the definition of a second strip type second conduction type diffusion zone, wherein, the first and the second strip second conduction type diffusion zones are not connected with each other; an annular second conduction type diffusion area is defined between the first and the second strip second conduction type diffusion zones; a first conduction type diffusion area is defined on the inner side of the annular second conduction type diffusion area; a first grid is defined between the first strip type second conduction type diffusion zone and the annular second conduction type diffusion area; a second grid is defined between the second strip type second conduction type diffusion zone and the annular second conduction type diffusion area.