Semiconductor device and manufacturing method thereof

A transistor structure that improves ESD withstand voltages is offered. A high impurity concentration drain layer is formed in a surface of an intermediate impurity concentration drain layer at a location separated from a drain-side end of a gate electrode. And a P-type impurity layer is formed in a surface of a substrate between the gate electrode and the high impurity concentration drain layer so as to surround the high impurity concentration drain layer. When a parasitic bipolar transistor is turned on by an abnormal surge, electrons travel from a source electrode to a drain electrode. Here, electrons travel dispersed in the manner to avoid a vicinity X of the surface of the substrate and travel through a deeper path to the drain electrode as indicated by arrows in FIG. 4.