High withstand voltage semiconductor device covered with resin and manufacturing method therefor

In the step of applying a sealing resin to a high withstand voltage semiconductor chip mounted on a package or substrate and hardening the same, the resin hardening is performed while applying a high voltage between at least either an electrode terminal connected with a wire, etc. to the chip or a chip electrode and another electrode requiring an insulation voltage endurance between the same and the above electrode terminal. As the sealing resin, use is made of a synthetic polymer compound consisting of, linked together three-dimensionally by covalent bonds, organosilicon polymers (C) formed by alternately linearly linking, by siloxane bonds, organosilicon polymers (A) having a crosslink structure by siloxane and organosilicon polymers (B) having a linearly linked structure by siloxane (Si-O-Si bonded matter). Thus, in the use of a high withstand voltage semiconductor chip mounted on a substrate or package and sealed with the resin, any increase of current leakage can be suppressed even when high inverse voltage is applied, thereby attaining a stable insulation power endurance agreeing with designed value.