A damascene copper wiring image sensor

A CMOS image sensor array (100) and method of fabrication wherein the sensor includes Copper (Cu) metallization levels (M1, M2) allowing for incorporation of a thinner interlevel dielectric stack (13 Oa-c) with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure (135a, 135b) formed at locations between each array pixel and, a barrier material layer (132a, 132b) is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening (51) is then refilled with dielectric material (150). Prior to depositing the refill dielectric, a layer of either reflective or absorptive material (140) is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode (18) or by eliminating light reflections.