Flash memory element

A flash memory device comprises a first group of dummy memory cells disposed between source selection transistors, which are coupled to a source selection line, and memory cells coupled to a first wordline. The flash memory device further comprises a second group of dummy memory cells disposed between drain selection transistors, which are coupled to a drain selection line, and memory cells coupled to the last wordline. The flash memory device is configured to prevent program disturbance in deselected cell strings and degradation of programming/erasing speeds in a selected cell string.