Method for fabricating an nrom memory cell array

In the method, trenches are etched and, in between, bit lines ( 8 ) are in each case arranged on doped source/drain regions ( 3, 4 ). Storage layers ( 5, 6, 7 ) are applied and gate electrodes ( 2 ) are arranged at the trench walls. After the introduction of polysilicon, which is provided for the gate electrodes ( 2 ), into the trenches, the top side is ground back in a planarizing manner until the top side of the covering layer ( 16 ) is reached, and afterward a polysilicon layer ( 18 ), which is provided for the word lines, is applied over the whole area and patterned to form the word lines.