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1,260,090. Automatic exchange systems. WESTERN ELECTRIC CO. Inc. 21 Oct., 1970 [21 Oct., 1969], No. 49931/70. Heading H4K. In a telephone exchange the control system comprises a data processing arrangement in which a program controlled processor and a wired logic processor share the same temporary m...

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Bibliographische Detailangaben
Hauptverfasser: MICHAEL QUINN,THOMAS, SALVATORE VIGILANTE,FRANK
Format: Patent
Sprache:ger
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Zusammenfassung:1,260,090. Automatic exchange systems. WESTERN ELECTRIC CO. Inc. 21 Oct., 1970 [21 Oct., 1969], No. 49931/70. Heading H4K. In a telephone exchange the control system comprises a data processing arrangement in which a program controlled processor and a wired logic processor share the same temporary memory, priority of access to the temporary memory alternating between the program controlled and wired logic processors. In basic operation cycles, referred to as minor cycles, the program control has priority of access in the first portion of each cycle while the wired logic has priority of access in the latter portions. The wired logic performs a portion of the digit receiving, digit sending, line scanning and data sending tasks. By assigning to the wired logic repetitive high rate functions for which accuracy of timing is required, program real-time is conserved. Moreover, program interrupts for the purpose of supervising telephone system input/output functions occur no more frequently than at 25 msec intervals. The processing machine cycle is 3 Ásec. and instruction implementation can take 1 to 6 such cycles while access to the temporary memory and peripheral access circuit may take 4 cycles at most. Whenever wired logic has access to the temporary memory the program control is barred and may in consequence stand idle for periods up to 9 Ásec. If a particular class of wired logic work remains unfinished at the end of a minor cycle the priority given to wired logic in accessing the temporary memory is extended into the next minor cycle and the program control is barred for a further fixed period sufficient to clear the backlog. Under the classification of non-deferrable quota work the wired logic processes data sending on 32 channels. In each minor cycle of 1À251 msec, the wired logic addresses the temporary memory to obtain two sixteen bit words, one bit corresponding to one of the 32 channels, so that data is sent at 800 bits/sec. Each data message sent comprises 64 serial bits. Data sending may be employed for the purpose of effecting control of remote subordinate offices. The exchange network uses reed relays and the conditions of 6576 lines are ascertained by eight duplicated scanners employing ferrod sensors after the manner of the Bell System No. 1 ESS. Line scanning is undertaken by the wired logic whenever it is not engaged with quota work and during times when neither the program nor the wired logic requires the peripheral access circuit. Scanning h