Anordnung zur optischen Darstellung von Information mit einer Bildschirmeinheit

1,109,987. Displaying data from stores. INTERNATIONAL BUSINESS MACHINES CORPORATION. 13 Jan., 1967 [25 March, 1966], No. 2055/67. Heading G4C and G4H. A cyclic trace display device e.g. a television display 33 (Fig. 1) is selectively fed with data from a cyclic buffer store 21, control means supplying data from every nth (e.g. 2nd) block location to the display, the blocks being displayed on successive lines. In the embodiment described data from a keyboard 10 is converted to video and binary coded decimal form in a composer 12 and parallel to serial converter 13 respectively and read in, on leads 20, 22 (Fig. 9), when a write pulse enables AND gates 116, 117, via OR gate 120 and sequentially enabled AND gates 121- 124, to one of four parallely connected delay lines 110-114. Output signals via AND gates 127-130 and OR gate 138 are supplied (1) to the T.V. display via an AND gate enabled except during vertical re-trace, (2) to marker bit control 55 and (3) to AND gate 119 for re-entry into the store. During the first cycle of the delay line blocks of data, 1, 2, ... 78 (Fig. 2) are displayed, blocks 79 to 143 being fed from the delay line during horizontal retrace. During the second cycle blocks 79 ... 143 are displayed and during vertical re-trace binary coded data in blocks KB1 ... KB12 is read out. During a write in operation marker bits are inserted-in the last bit of the last byte of data-the marker bit control 55 prior to a writing operation destroying old marker bits. When the marker bit control locates a binary coded decimal marker bit during vertical retrace the output of OR gate 134 becomes positive and a bit counter is then enabled to start read in of data, the AND gate 119 being closed to prevent re-entry of the marker bit. The delay lines may be cleared by depressing switch 140 and before new data is read in one initial marker bit is inserted in each block in the last bit position by depressing switch 144 which allows properly timed pulses on line 145 to be stored. When data is written in the initial marker bit is destroyed.