PULSE TRANSFORMING CIRCUIT ARRANGEMENTS USING A CLOCK PULSE RESPONSIVE DELAYED INVERTER MEANS

In a pulse transforming circuit arrangement for generating pulses responsive to the rise and/or fall of an input pulse signal, there is used a clock pulse responsive delayed inverting circuit which inverts the input signal at a point of time delayed from the level change of the input signal for a period corresponding to the width of the clock pulse, in accordance with the level of the clock pulse which changes in synchronization with the level change of the input signal. The clock pulse responsive delayed inverting circuit may be constituted by a clocked inverter. A NAND gate and/or a NOR gate generate pulses responding to the level variation of the input signal since the level of an output signal from the clocked inverter and the changed level of the input signal coincide with each other for a period corresponding to the width of the clock pulse.