SELF-ALIGNED FIELD EFFECT TRANSISTOR AND CHARGE-COUPLED DEVICE

A semiconductor device containing in a single semiconductor body a self-aligned Field Effect Transistor and a Charge-Coupled Array having an improved capacity for storing charges. The device is formed by depositing both polysilicon and silicon nitride layers over a silicon dioxide layer on the surface of a silicon body and selectively etching these layers so that suitable dopants may be diffused or ion-implanted into selected areas of the underlying silicon body to form, in the same semiconductor body, an improved charge-coupled array having an improved self-aligned Field Effect Transistor associated therewith. This process not only results in a device in which the chance of an inversion layer under the oxide on the surface of the device is substantially reduced, but also provides a self-aligned Field Effect Transistor having a thinner gate oxide and a charge-coupled array that has an increased capacity for storing charges. The improved array so formed also has, during operation, zero spaced depletion regions so that unwanted electrical discontinuities between or within the depletion regions of the charge-coupled array are avoided. Because zero spacing is achieved by using these thin conducting layers, the metal phase lines can be made narrow thus leaving openings in the charge transfer channel making the device particularly suitable for imaging applications.