INERT ENVIRONMENT FUSIBLE LINKS

A micro-fuse assembly includes a substrate, a number of thin-film micro-fuses on the substrate, and a topping wafer configured to sealingly engage to at least one of the substrate or the thin-film micro-fuses to define a cavity therebetween. The cavity is configured to encapsulate the thin-film micr...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: BACKMAN, ROGER ALAN, POTASEK, DAVID P
Format: Patent
Sprache:eng ; fre
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Beschreibung
Zusammenfassung:A micro-fuse assembly includes a substrate, a number of thin-film micro-fuses on the substrate, and a topping wafer configured to sealingly engage to at least one of the substrate or the thin-film micro-fuses to define a cavity therebetween. The cavity is configured to encapsulate the thin-film micro-fuses within an inert environment sealed within the cavity. A method of encapsulating a micro-fuse assembly within an inert environment using a topping wafer is also disclosed.