SYNCHRONIZED MULTI-OUTPUT DIGITAL CLOCK MANAGER

A digital clock manager is provided. The digital clock manager generates an output clock signal that causes a skewed clock signal to be synchonized with a reference clock signal. Furthermore, the digital clock manager generates a frequency adjusted clock signal that is synchronized with the output c...

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Bibliographische Detailangaben
Hauptverfasser:	LOGUE, JOHN D, PERCEY, ANDREW K, GOETTING, F. ERICH
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:	A digital clock manager is provided. The digital clock manager generates an output clock signal that causes a skewed clock signal to be synchonized with a reference clock signal. Furthermore, the digital clock manager generates a frequency adjusted clock signal that is synchronized with the output clock signal during concurrence periods. The digital clock manager includes a dela y lock loop and a digital frequency synthesizer. The delay lock loop and a digital frequency synthesizer. The output clock signal lags the synchrozing clock signal by a DLL output delay. Similarly, the frequency adjusted clock signal lags the synchronizing clock signal by a DFS output delay. By matchin g the DLL output delay to the DFS output delay, the digital clock manager synchronizes the output clock signal and the frequency adjusted clock signal .