DIGITAL PROCESSING DEVICE

A digital processing device P, generally configured as a regular tree with n +1 levels S0, S1, S2...Sn and degree k, is provided in the form of a circuit Pn on the level Sn and forms the root node of the tree, an underlying level Sn- q, q=1,2,...n-1, in the circuit P comprising generally kq circuits Pn-q provide d nested in the kq-1 circuits Pn-q+1 on the overlying level Sn-q+1, each circu it Pn-q+1 on this level comprising k circuits Pn-q. A for q=n defined zeroth level in the circuit Pn comprises from kn-1+1 to kn circuits P0 which form kernel processors in the processing device P and on the level S0 constitute the leaf nodes of the tree, the kernel processor P0 being provided nested in a number from 1 to k in each of the circuits P1 on the level S1. Each of the circuits P1, P2, ...Pn, comprises a logic unit E which generally is connecte d with circuits P0, P1,...Pn-1 provided nested in the former circuits on the nearest underlying level and is additionally adapted to connect nodes on the same or underlying levels in neighbour trees. Each of the circuits P0, P1,...Pn has additionally identical interfaces I, such that IP0=IP1=...IPn.< /SDOAB>