METHOD AND APPARATUS FOR REDUCING TRANSISTOR AMPLIFIER HYSTERESIS

The present invention provides a biasing method and apparatus which provides bias circuits of radio frequency (RF) power transistors with a low reactive impedance at low frequencies to reduce hysteresis related distortio n without affecting the transistor input or output impedance or any impedance matching network which may be used. In one embodiment, the invention is incorporated in a lateral diffused metal-oxide semiconductor (LDMOS) transistor to reduce hysteresis brought about by a drain bias circuit withou t any impact on the transistor output impedance. By removing the effect of the bias circuit at RF frequencies, the bias circuit can be designed with a low reactive impedance at low frequencies without any material consequences on the transistor output impedance. With a low enough reactive impedance, the hysteresis introduced by the bias circuit is substantially reduced. An auxiliary bias feed external to an RF transistor package is also embodied.