SYSTEM BUS CONTROL SYSTEM IN A MULTI-PROCESSOR SYSTEM

The first invention relates to a multi-processor system in which a bus arbiter permits an answer transfer request to utilize a bus utilization right with higher priority than a command transfer request, thereby increasing the processing efficiency of CPU boards. The second invention relates to a multi-processor system utilizing a system bus of a time split transfer system in which a data width of its own unit is inserted into a command and an answer transmitted and received between the processors and transmitted as bus width information, thus making it possible to interconnect a unit, which processes data of an arbitrary data width, to the system bus. In accordance with the third invention, local memories of a plurality of units connected to the system bus can be accessed via a bus interface of an input and output unit.