FAIL-FAST, FAIL-FUNCTIONAL, FAULT-TOLERANT MULTIPROCESSOR SYSTEM
A multiprocessor system includes a number of subprocessor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of...
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| creator | HORST, ROBERT W JONES, CURTIS WILLARD JR BAKER, WILLIAM EDWARD DREXLER, BARRY LEE GARCIA, DAVID J ISWANDHI, GEOFFREY I BROWN, JOHN MICHAEL MEYERS, STEVEN C BRUCKERT, WILLIAM F CUTTS, RICHARD W., JR CAMPBELL, GARY F WHITESIDE, PATRICIA L ELROD, HARRY FRANK KRAUSE, JOHN C MEREDITH, SUSAN STONE WATSON, WILLIAM JOEL JEWETT, DOUGLAS EUGENE CODDINGTON, JOHN DEANE SONNIER, DAVID P BUNTON, WILLIAM PATTERSON FOWLER, DANIEL L WILLIAMS, FRANK A ZALZALA, LINDA ELLEN LOW, STEPHEN G KLECKA, JAMES STEVENS BANTON, RANDALL G HINTIKKA, PAUL N |
| description | A multiprocessor system includes a number of subprocessor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied. |
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A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.</description><edition>6</edition><language>eng ; fre</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1996</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19961208&DB=EPODOC&CC=CA&NR=2178440A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25555,76308</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19961208&DB=EPODOC&CC=CA&NR=2178440A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HORST, ROBERT W</creatorcontrib><creatorcontrib>JONES, CURTIS WILLARD JR</creatorcontrib><creatorcontrib>BAKER, WILLIAM EDWARD</creatorcontrib><creatorcontrib>DREXLER, BARRY LEE</creatorcontrib><creatorcontrib>GARCIA, DAVID J</creatorcontrib><creatorcontrib>ISWANDHI, GEOFFREY I</creatorcontrib><creatorcontrib>BROWN, JOHN MICHAEL</creatorcontrib><creatorcontrib>MEYERS, STEVEN C</creatorcontrib><creatorcontrib>BRUCKERT, WILLIAM F</creatorcontrib><creatorcontrib>CUTTS, RICHARD W., JR</creatorcontrib><creatorcontrib>CAMPBELL, GARY F</creatorcontrib><creatorcontrib>WHITESIDE, PATRICIA L</creatorcontrib><creatorcontrib>ELROD, HARRY FRANK</creatorcontrib><creatorcontrib>KRAUSE, JOHN C</creatorcontrib><creatorcontrib>MEREDITH, SUSAN STONE</creatorcontrib><creatorcontrib>WATSON, WILLIAM JOEL</creatorcontrib><creatorcontrib>JEWETT, DOUGLAS EUGENE</creatorcontrib><creatorcontrib>CODDINGTON, JOHN DEANE</creatorcontrib><creatorcontrib>SONNIER, DAVID P</creatorcontrib><creatorcontrib>BUNTON, WILLIAM PATTERSON</creatorcontrib><creatorcontrib>FOWLER, DANIEL L</creatorcontrib><creatorcontrib>WILLIAMS, FRANK A</creatorcontrib><creatorcontrib>ZALZALA, LINDA ELLEN</creatorcontrib><creatorcontrib>LOW, STEPHEN G</creatorcontrib><creatorcontrib>KLECKA, JAMES STEVENS</creatorcontrib><creatorcontrib>BANTON, RANDALL G</creatorcontrib><creatorcontrib>HINTIKKA, PAUL N</creatorcontrib><title>FAIL-FAST, FAIL-FUNCTIONAL, FAULT-TOLERANT MULTIPROCESSOR SYSTEM</title><description>A multiprocessor system includes a number of subprocessor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. 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A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | FAIL-FAST, FAIL-FUNCTIONAL, FAULT-TOLERANT MULTIPROCESSOR SYSTEM |
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