CLOCK PHASE ALIGNMENT

A phase error integrator (11) for determining the phase error between a data signal and a clock signal frequency locked to the data signal has a data input and a clock input. In one embodiment the phase error integrator (11) is formed as two functional components, namely a phase error detector (20) and an integrator chain (21). The phase error detector (20) sends to the integrator (21) one of two output signals (NAR, NAL) depending on whether the phase error is positive or negative. The integrator chain has a number of outputs (ERR0-ERR13) the first half of which initially have a binary 1 and the second half of which initially have a binary 0. Depending on which output signal arrives from the phase error detector the binary 1's shift right or the binary 0's shift left. The integrator may be combined with a delay block (15) connected to the outputs of the integrator chain (21). The data signal is fed to the delay block (15) and a delayed data output signal is obtained which is connected to the data input of the phase error integrator (11). The delay block (15) delays the data signal until there is concordance between the phase of the clock and delayed data signals.