High Value Resistive Load for an Integrated Circuit

A linear and symmetrical gigaohm resistive load structure for an integrated circuit is implemented using a thin film accumulation mode MOSFET configured as a split gate symmetrically off device. Preferably, the resistive load structure comprises two thin film accumulation mode field effect transistors connected in series with a common node and separate gate electrodes. The thin film devices are provided with undoped or lightly doped polysilicon channel regions to provide a desired gigaohm resistance value. By connecting each of the two gate electrodes to the respective source terminals, a two terminal gigaohm resistor structure is produced in which one of the devices is always in the high impedance OFF state regardless of the terminal voltages. The split gate structure allows the integration of the device with minimal metallization interconnect and only two terminals.